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Formal Checkers
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Description
Formal Checkers is an application development tool which helps you in creating simulation monitors, coverage analysis in order to track the occurrence of events of interest during the simulation. These checkers are used to monitor the simulation results on a cycle by cycle basis for violation of the properties. It is capable of producing code in C++, VHDL and Verilog and also supports ModelSim of Model Technology, Sugar 2(EDL flavor).
Information
| Title: | Formal Checkers |
| Author: | admin0042 |
| Price / Cost: | Commercial |
| Platform / OS: | Linux, Solaris, AIX |
| Version: | 1.05 |
| Last Updated: | 2004-05-08 |
| URL: | Click to Visit |
| Download URL: | Click to Download |
| Web site Language: | English |
| Total Votes: | 1 |
| Current Rating: | 0.00 |
| Total Hits #: | 63 |
| Listings ID #: | 23753 |
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